Slide 1
To implement classification, we are just adding some analog components on top of a standard 6T SRAM array
Our input is 81 pixel image with 5b per pixel. Each WLDAC takes in a pixel and converts it to an analog voltage.

Depending on the weight stored in the SRAM cell, one of the differential bit lines will discharge (multiply by 1 or -1).

All bit-cells are performing this operation in parallel, so in each column you get the weighted sum on the differential bit-lines.

The comparator uses differential bit-lines to present a classification for the column.

Slide 2
When classify mode is enabled, the word-line DAC generates a current representing the input pixel. The current is pulled down by a scaled up bit-cell from the SRAM array which generates a WL voltage
This forms a current mirror with each bit cell, which will discharge one of the differential bit-lines by a proportional current.