manual: ECE1390 RF A1 - Low Noise Amplifier.pdf
repo: https://gitea.nodusk.me/jay/2025-meng-ece1390-rf
report: ECE1390 RF A1 - Report.pdf

ECE1390 RF R - Report Example.pdf
ECE1390 RF L5 - Low Noise Amplifier
RF Microelectronics

The goal of a Low Noise Amplifier (LNA) is to boost a weak incoming signal while adding as little Noise as possible. In other words, minimize the ratio of SNR at the input to the SNR at the output, this is called the Noise Figure (nf).

Transmission lines and antennas are generally designed with 50 Output Impedance (). To minimize reflections at the input to the low noise amplifier at Radio Frequency (RF), the Input Impedance () must also be designed to 50. Since the gates of MOSFETs are Capacitive, the input impedance is large, making traditional amplifier architectures less effective.

One solution is to use a Common-Source Amplifier and place a Shunt Resistor at the input to form a resistive matching network. This isn't a great solution as Resistors are very noisy and the Noise Figure exceeds 3dB, defeating the purpose of a low noise amplifier.

In a Common-Gate Amplifier the input is at the source of the input MOSFET, which gives . Input matching can be achieved by just sizing and biasing the MOSFET appropriately, though it is important to note that and bias current must be large to achieve 50. When , the noise figure is about 3dB. NF can be further reduced by increasing even more, sacrificing power and input matching.

Another option is an Inductor degenerated Common-Source Amplifier. The source degeneration inductor resonates with of the input MOSFET, which leave a primarily real resistance at the Resonance Frequency. For perfect matching, the inductor must be large. This problem can be alleviated by adding an off-chip series gate inductor. Noise figure can be low with minimal power consumption, just with slightly worse and more complex input matching.

where,

source: RF Microelectronics

In this design, a single-stage cascade common-source LNA topology with inductive source degeneration, is chosen to achieve the desired performance metrics. For input matching of the CS LNA, the following must hold true

Assuming is a bond wire with an inductance of 0.5 , and is 5 ,

With a simple parametric analysis, this gm and ft is achieved with a 44/40 device with 1.6mA of bias current. A channel length of 40nm was used to reduce short channel effects. Putting this design together shows a S11 of -21dB @ 7.2GHz. To reduce the center frequency, the device width can be increased to in turn increase . A width of 50 results in a S11 of -21.4dB @ 7GHz. The bandwidth achieved is 270MHz. Note that increasing the bias current can improve the S11 and bandwidth without adjusting the center frequency, but is unnecessary in this case since matching. May need to reconsider if more output gain is needed.

At the output of the LNA, and form an LC tank resonate to maximize the gain at the desired . The LC tank is also in parallel with and of cascode MOSFET. The latter is assumed to be much smaller and not considered.

The gain is lower than expected, at about 13dB @ 7GHz. As noted earlier, increasing the bias current to 2.5mA improves the gain to above 14.3dB.

The testbench consists of two ports from analogLib, 1 ac coupling capacitors, and the mixer load capacitance.

Port 0

Port 1

Variables

Choosing Analyses

Direct Plot Form

Choosing Analyses

run pss simulation

Direct Plot Form

run pss and pac simulation

Direct Plot Form

Choosing Analyses

Direct Plot Form

processed with Pandas and Matplotlib, see git repo