ECE1398 L3 - CMOS Fabrication Flow.pdf

Non Self-Aligned MOSFET

  • traditional non-self-aligned gate needs to be oversized and can lead to higher resistance and capacitance in the MOSFET

Flow

  1. Implant p-well with p-field mask
  2. Use wet-oxidation to grow thick oxide
  3. Etch oxide and implant n+ or p+ S/D/B regions. Thin oxide is grown during drive in.
  4. Etch oxide in device area
  5. Grow thin gate oxide, open contact holes and perform metallization

Self-Aligned MOSFET

  • new self-aligned gate has limit of 20nm

Flow

  1. Implant p-epitaxial growth and p-well with p-field mask
  2. Grow thin pad oxide and deposit silicon-nitride
  3. LOCOS oxidation is performed, silicon-nitride protects covered
  4. Wet etch silicon nitride using timed etch, also removes pad oxide
  5. Clean and grow gate oxide, then deposit polysilicon layer
    • sometimes Vth adjustment happens before
  6. Deposit thick oxide layer, timed RIE etch is used to remove it
    • side-wall spacer remains, this protects the n-LDD region from more implants
  7. Implant S/D/B regions
  8. Deposit thick oxide layer, etch contact holes, and perform metallization
  9. Silicon-nitride layer used to seal wafer

Integrated Resistors

N-well

  • depth and concentrations fixed by process
  • p-well and p-sub not a good choice since they are shorted to GND
  • resistor voltage must remain positive
  • Large voltage will increase depletion region and add capacitance between n-well and GND. Use n+ diffusions resistor to decrease this effect
  • p+ diffusion can be used but narrow depletion region will lead to large capacitance
  • pinched n+/p+ can be used for higher resistance

Polysilicon

  • poly layer ontop of thick oxide minimizes cap and has large resistance
  • isolated from substrate so negative swing possible

Integrated Capacitors

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  • junction cap between nwell and psub. bottom gnd
    • very high VC
  • mos cap between metal and pwell. bottom gnd
    • very high VC for p-well
  • use n+ diffusion to reduce VC and increase voltage swing
  • inter-poly has best parameters

Ohmic Contacts

  • metal work function must be smaller than n-type semiconductor, or larger for p-type
  • better to increase doping to match work functions. lower it for n-type, raise for p-type

Lambda Rules

  • Needs to provide sufficient:
    • separation under worst case lateral diffusion (4)
    • coverage under worst case mis-alignment (2)
  • use consistent size for small geometries to ensure uniform exposure

Antenna Rule

  • RIE applies intense RF field, long MOS capacitor like structure will pick up charges and damage oxide.
    • Frequency of field
  • gate area over oxide vs gate area over transistor must be kept below limit
  • break long interconnects with metal

Electromigration Rules

  • Al can carry few for 1 thick metal
  • Electromigration happens when metal ions are displaced by large electric field
  • Solutions:
    • avoid 90 bends
    • wider metal
    • copper
    • metal slotting

MOSFET Layout

Minimum Parasitics

  • multi-fingered
    • better
    • good for differential circuits
  • corrugated
    • lower capacitance from parallel plate
    • current crowding

Capacitor and Resistor Layout

  • minimize perimeter:

  • use unit sizes

  • common centroid for ratios

BJT

Typical CMOS Flow

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Parasitic Transistor

  • p-field increases the vth of transistor formed between n-well + n+ / p-well + n+ intersection