ECE1398 L6 - Small Geometry Devices.pdf

Scaling

MOS scale at 0.7x/cycle or 0.5x/2 cycles

Future Devices

Challenges

  • Lithography, device, and interconnect scaling
  • Design and knowledge, critical dimension control, reliability

Parameters

  • limited to 200mV due to subthreshold leakage. limited to 1V
  • = 1/50 to 1/25 of channel length. Vulnerable to quantum tunneling
  • Doped poly gates are used to reduce below 300mV
  • Super Halo: non-uniform channel profile

Advanced CMOS

  • shallow trench iso, 1.5-2nm gate ox, LDD, doped poly, self aligned contacts

Gate Leakage

Lithography

  • minimum length 2x wavelength
  • Optical projection printing limited to g-line and i-line (436nm and 365nm)
  • Excimer lasers operate at 248nm
  • resolution enhancements allow 1/2 wavelength as feature size

  • Use smaller exposure pattern to minimize proximity effect
  • Scalpel: Scattering with Angular Limitation Projection Electron-beam Lithography
    • reduces image projection
    • electrons scattered weakly by membrane mask and strongly by masking pattern. masking pattern blocks electrons

Interconnection

  • high resistive and capacitive losses
  • copper > aluminium because of lower resistivity and better electromigration limit
  • next goal is low k dielectric for insulation to reduce C
  • repeaters for long signal lines

Testing

  • a

Short Channel Effect

  • channel pinch off causes rise in as increases
  • more prominent for small L

Sub-threshold Conduction

  • parasitic BJT dominates for small L
  • carrier diffusion current from S to D in sub

Threshold Variations

  • affected by both channel length and width

Thin-body Transistors

  • Ultra-thin body has high resistance.
    • Grow thicker Si layer at S and D
    • Limited to 12nm
  • Double-Gate - FINFET
    • etch silicon
    • fixed finger dimensions
    • Si orientation determines mobility
    • DVS and DVTS can be used to reduce
  • Back-Gated