Static Timing Analysis
Method to determine if timing constraints are met for all paths in a design under worst case scenario.
Constraints
- Setup Time: time that data must arrive before the clock edge
- Hold Time: time that data must remain after the clock edge
- violations cause Flip-Flop go Metastable and capture wrong data
Concepts
- timing path: sequence of elements from a start-point to end-point
- delays:
- cell delay: Propagation Delay through logic gates
- net delay: delay due to interconnects
- slack: difference between required time and arrival time (negative is bad)